By Pui-In Mak, Ben U Seng Pan, Rui Paulo Martins
With the previous few decade efforts on lithography and integrated-circuit (IC) applied sciences, very inexpensive microsystems were effectively constructed for plenty of diversified functions. the craze in instant communications is towards making a networkubiquitous period within the future years. Many unheard of possibilities and demanding situations, comparable to layout for multi-standardability and low-voltage (LV) compliance, are quickly changing into the mainstream instructions in wireless-IC study and improvement, on condition that the previous can supply the easiest connectivity between diverse networks, whereas the latter can facilitate the expertise migration into the sub-1-V nanoscale regimes for extra fee and gear relief.
Analog-Baseband Architecturees and Circuits presents architectural and circuit recommendations for instant transceivers to accomplish multistandard and low-voltage compliance. the 1st a part of the ebook studies the actual layer requisites of recent instant communique criteria, provides the basic tradeoffs concerned about transceiver structure choice, and gives case experiences of the state of the art multistandard transceivers, the place the major suggestions bolstered are highlighted and mentioned. A statistical precis (with a hundred+ references pointed out) of so much used transmitter and receiver architectures for contemporary conversation criteria is equipped. all of the references are citied from the prime boards, i.e., ISSCC, CICC, VLSI and ESSCIRC, from 1997 to 2005.
The moment half specializes in the architectural layout of multistandard transceivers. A coarse-RF fine-IF (two-step) channelselection approach is disclosed. It, throughout the reconfiguration of receiver and transmitter analog basebands, allows not just a rest of the RF frequency synthesizer’s and native oscillator’s layout requisites, but additionally an effective multistandard compliance by means of synthesizing the low-IF and zero-IF within the receiver; and the direct-up and two-step-up within the transmitter. the main is verified in few layout examples. one in all them is a system-in-a-package (SiP) receiver analog baseband for IEEE 802.11a/b/g WLAN. It not just has the two-step channel choice embedded, but in addition includes a flexible-IF topology, a different 3D-stack floorplan, and a specific layout technique for top testability and routability.
The 3rd half offers with the circuit layout. as well as the methodical description of many LV circuit recommendations, three tailormade LV-robust practical blocks are offered. They contain: 1) a double-quadrature-downconversion filter out (DQDF) – it realizes simultaneously clock-rate-defined IF reception, I/Q demodulation, IF channel choice and baseband filtering. 2) A switched-current-resistor (SCR) programmable-gain amplifier (PGA) – it bargains a transient-free constant-bandwidth achieve adjustment. three) An inside-OpAmp dc-offset canceler – it saves the silicon sector required for knowing a wide time consistent on chip whereas maximizing its highpass-pole switchability for speedy dc-offset transient.
The final half provides experimental result of the three tailored construction blocks and a fully-integrated analog-baseband IC fabricated in a standard-VTH CMOS approach. formerly untold on-/off-chip co-setup for either full-chip and development blocks measurements are defined. not just the development blocks have effectively prolonged the cutting-edge boundary when it comes to sign bandwidth and provide voltage, the analog-baseband IC has been to date the lowest-voltage-reported resolution for IEEE 802.11a/b/g WLAN receivers.
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Extra resources for Analog-Baseband Architectures And Circuits For Multistandard And Lowvoltage Wireless Transceivers
2002. [ZIF/DU] E. , “A Fully Integrated Zero-IF Transceiver for GSM-GPRS Quad Band Application,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 274–275, Feb. 2003. [ZIF/DU] E. , “A Quad-Band Low-Power Single-Chip Direct-Conversion CMOS Transceiver with ΣΔ-modulation loop for GSM,” in Proc. European Solid-State Circuits Conference (ESSCIRC), pp. 217–220, Sept. 2003. [ZIF/DU] J. 18μm Standard CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp.
The strength of the signal is indicated by a receiver signal strength indicator (RSSI). One frequency synthesizer with VCO is used between different modes, and the receiver and transmitter. Low-dropout voltage (LDO) regulators are embedded. Figure 2-16. T. 11a/b/g transceiver Discussion – Table 2-10 summarizes the performances of the three TXRs, R. 11a/b/g such that the problem of LO-to-LO self-mixing is reduced, whereas the IF and BB circuitries are shared. Z. Xu’s transceiver directly downconverts the signal to Chapter 2: Transceiver Architecture Selection 31 the BB, resulting in very low power and area consumption.
T. 5V 28mA Fully-Integrated Fast-Locking Quad-Band GSMGPRS Transmitter with Digital Auto-Calibration in 130nm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 188–189, Feb. 2004. 21] M. , “A Polar Modulator Transmitter for EDGE,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 190–191, Feb. 2004. 22] A. , “A highly Integrated Quad Band Low EVM Polar Modulation Transmitter for GSM/EDGE Applications,” in Proc.